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ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
mclock
- 用VHDL编写的带闹钟报时功能的数字钟 ,现代数字系统设计作业。 采用文本图形混合输入,在maxplus2 10.0运行通过-Written by VHDL figures with alarm chime clock, modern digital system design work. Graphics mixed with text input, run by the maxplus2 10.0
fpgaclock
- 数字钟小程序,FPGA程序,用VHDL编写的源程序-failed to translate
shuzizhong
- 基于VHDL的数字钟,可以整点报时和校准时间-VHDL CPLD
clock
- vhdl 简易数字钟 基于fpga 使用quartus7.0,便于移植到其他平台
watch
- 本文件为电子设计而开发的多功能数字钟VHDL语言完整源代码 --该数字钟实现的功能有时间,秒表,闹钟,年月日的显示设置等 -This document is multi-functional electronic design and development of a complete VHDL, digital clock source code- the digital clock function can be achieved time, stopwatch, alarm clo
music1
- VHDL 多功能数字钟源码音乐模块2,自扒简谱-Multi-function digital clock source VHDL music module 2, since the expense of musical notation
shuzizhong
- 这个是关于用VHDL语言设计出来数字钟的程序,能够实现最基本的功能,对于想学习VHDL语言的人来说,是一个很好练习的例子。-This is about the design using VHDL, digital clock out of the program, to achieve the most basic functions, for people who want to learn VHDL language, it is a good practice example.
clock1
- 本程序用VHDL编写数字钟,具有定点报时,手动调整时间等功能,能下载到板子上显示时间。-This program written by VHDL digital clock, with a fixed broadcast, manually adjust the time and other functions, can be downloaded to display the time on the board.
clock
- VHDL编程--数字钟 非常适合初学者-VHDL Programming- digital clock is ideal for beginners
clock
- 在FPGA下用VHDL语言设计的数字钟程序-Under the FPGA design using VHDL, digital clock program
shizhong
- vhdl描述的数字钟,功能一样,方法不同-vhdl descr iption of the digital clock, the same function, different methods
watch
- EDA数字钟VHDL的程序,它分多个模块进行,主要是采用VHDL语言而不是Verlog语言-the program for digital clock of EDA
8952
- 这是一个基于VHDL语言的数字钟设计,它是EDA的一个实例-This is a program for clock ,it is a example for EDA.
zs_clock
- 基于VHDL语言设计的电子钟,综合运用EDA技术,完成一个多功能数字钟设计-VHDL language design based on the electronic clock, integrated use of EDA techniques to complete the design of a multi-functional digital clock
clock
- 用VHDL 语言设计数字钟,实现在数码管上显示分钟和秒,并且可以手动调节分钟, 实现分钟的增或者减。该设计包括以下几个部分: (1)分频电路的设计,产生1Hz 的时钟信号,作为秒计时脉冲; (2)手动调节电路,包括“时增”“时减”“分增”“分减”。 (3)时分秒计时电路。 (4)7 段数码管显示电路。-Design with VHDL, digital clock, to achieve in the digital display minutes and seconds,
clock
- 用VHDL实现多功能数字钟 闹铃 计时 动显 报时等-VHDL realization of multi-functional digital clock with alarm timer was timekeeping and other fixed
sy6
- 数字钟的VHDL源程序,里面附有数字钟的VHDL源程序和原理图的数字钟电路,数字钟有en,clk,clr等接口。-Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
eclock
- 数字钟 分模块设计 实现基础功能 VHDL编写 -eclock vhdl
FPGAVHDLeclock
- 数字钟设计报告 包括源码 仿真 设计原理等 vhdl编写 -vhdl fpga eclock